1. Field of the Invention
The present invention relates generally to a semiconductor structure and process thereof, and more specifically to a semiconductor structure and process thereof, which forms a silicon and oxygen—containing metal layer on a metal gate.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). With the trend towards scaling down the size of semiconductor devices, however, conventional poly-silicon gates face problems such as inferior performance due to boron penetration and unavoidable depletion effect. This increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals that are suitable for use as the high-K gate dielectric layer are used to replace the conventional poly-silicon gate to be the control electrode. This control electrode of work function metals constitutes a metal gate.
In general, the method of replacing a conventional poly-silicon gate with a metal gate includes: removing the conventional poly-silicon gate and therefore forming a recess in an interdielectric layer; sequentially filling work function metals in the recess, that would cover the interdielectric layer as well. Thus, a planarization process would be performed to planarize the work function metals out of the recess and covering the interdielectric layer until the interdielectric layer is exposed, and the metal gate in the recess is formed. After the metal gate is formed, another dielectric layer will cover the interdielectric layer and the metal gate for forming interconnections above the metal gate and the interdielectric layer.
The above said planarization process may be a chemical mechanical polishing (CMP) process. In the semiconductor industry, chemical mechanical polishing (CMP) is the most common and important planarization tool applied. For example, the CMP process can be used to remove a topographical target of a thin film layer on a semiconductor wafer. The CMP process produces a wafer with both a regular and planar surface, to ensure a depth of focus (DOF) in the following photo process. In a CMP process, slurry is provided in a surface subject to planarization, and a mechanical polishing process is performed on the surface of the wafer. The slurry includes chemical agents and abrasives. The chemical agents maybe PH buffers, oxidants, surfactants or the like, and the abrasives may be silica, alumina, zirconium oxide, or the like. The chemical reactions evoked by the chemical agents and the abrasion between the wafer, the abrasives, and the polishing pad can planarize the surface of the wafer.
Moreover, after the metal gate is formed by the planarization process, another dielectric layer will cover the interdielectric layer and the metal gate. The interface between the interdielectric layer and the metal gate plays an important rule for performances.